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RoCC accelerator interface for different RISC-V cores
3 messages
Hi Chip alliance Group, I have recently joined the group and I am presently working on my academic projects on RISC-V extension and creating projects for distributed system. One of them is to implemen
Hi Chip alliance Group, I have recently joined the group and I am presently working on my academic projects on RISC-V extension and creating projects for distributed system. One of them is to implemen
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By
Hena Naaz
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Bitmanip instructions in riscv-dv isn't generating any of Zbb, Zbs, Zba instructions
Hi, I was trying to generate Bitmanip test in riscv-dv setup. Run command used: python run.py --target rv32imcb --test riscv_b_ext_test --simulator vcs --steps gen Tried following iterations: -> targe
Hi, I was trying to generate Bitmanip test in riscv-dv setup. Run command used: python run.py --target rv32imcb --test riscv_b_ext_test --simulator vcs --steps gen Tried following iterations: -> targe
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By
Kumar R
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How do I connect the systemverilog design files to the the test and run the test?
3 messages
Hi, A newbie HW person here! I've installed the RV toolchain, spike disassembler from SiFive site and cloned the rv-dv repo. I don't know how to connect the test to my SV design file, and how do I get
Hi, A newbie HW person here! I've installed the RV toolchain, spike disassembler from SiFive site and cloned the rv-dv repo. I don't know how to connect the test to my SV design file, and how do I get
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By
user01206
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RISCV-DV basic test not working with OVPSIM/OVPSIMPLUS
12 messages
Hi, I'm trying to explore riscv-dv openly available in GitHub. I tried to run basic test arithmetic_basic_test available. I can see .S,.bin,.o getting generated. I'm unable to run this during step iss
Hi, I'm trying to explore riscv-dv openly available in GitHub. I tried to run basic test arithmetic_basic_test available. I can see .S,.bin,.o getting generated. I'm unable to run this during step iss
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By
Kumar R
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Building a UVM Test Bench using the Google Risc-v dv generator and spike/imperas simulator
2 messages
Hi All, I like to verify a risc-v cpu using the google risc-v-dv generatior and riscOVPsim simulator. The risc-v dv generator gives some UVM code that can be run to generate the .asm files. But im not
Hi All, I like to verify a risc-v cpu using the google risc-v-dv generatior and riscOVPsim simulator. The risc-v dv generator gives some UVM code that can be run to generate the .asm files. But im not
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By
pranavrm@...
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GOOGLE RISC-V DV
Greetings, I have joined this group to get started with Risc-V DV. I wanted to understand the inside-out of Google Risc-V DV. If you could help me out, it would be greatly appreciated. Kindly reply if
Greetings, I have joined this group to get started with Risc-V DV. I wanted to understand the inside-out of Google Risc-V DV. If you could help me out, it would be greatly appreciated. Kindly reply if
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By
Kinza Kinza
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Cancelling 4/2/2021 meeting
Since we had the CHIPS Alliance workshop this week we'll cancel the riscv-dv WG. PTAL at the workshop video and slides to catch up on what's going on in CHIPS Alliance. Slides: https://events.linuxfou
Since we had the CHIPS Alliance workshop this week we'll cancel the riscv-dv WG. PTAL at the workshop video and slides to catch up on what's going on in CHIPS Alliance. Slides: https://events.linuxfou
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By
Matt Cockrell
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3/19 meeting is on
Hi all - we will meet today. We are presenting an update on the workgroup in the 3/30 CHIPS Alliance Spring Workshop, I would like to solicit the group for feedback and who/what is using the tool.
Hi all - we will meet today. We are presenting an update on the workgroup in the 3/30 CHIPS Alliance Spring Workshop, I would like to solicit the group for feedback and who/what is using the tool.
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By
Matt Cockrell
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Canceling 2/19 Meeting
No agenda items. Cancelling this week.
No agenda items. Cancelling this week.
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By
Matt Cockrell
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Meeting 2/5/2021
We will be meeting tomorrow. The agenda includes presenters from OpenHW Group and Silicon Labs on their use of riscv-dv. Mike Thompson (OpenHW Group) Steve Richmond (Silicon Labs) Thanks - Matt
We will be meeting tomorrow. The agenda includes presenters from OpenHW Group and Silicon Labs on their use of riscv-dv. Mike Thompson (OpenHW Group) Steve Richmond (Silicon Labs) Thanks - Matt
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By
Matt Cockrell
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Meeting 1-8-2021
We are meeting 1-8-2021. The link to meeting here. Olof Kindgren will giving an overview of edalize.
We are meeting 1-8-2021. The link to meeting here. Olof Kindgren will giving an overview of edalize.
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By
Matt Cockrell
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Cancelling 12/11 Meeting
Tao and I both have conflicts and our scheduled presenter is unavailable, also had the RISC-V Summit this week. Next meeting on 1/8/21. Happy new year everyone. -- Matt
Tao and I both have conflicts and our scheduled presenter is unavailable, also had the RISC-V Summit this week. Next meeting on 1/8/21. Happy new year everyone. -- Matt
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By
Matt Cockrell
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Cancelling 10/30 Meeting
We'll see you on 11/13.
By
Matt Cockrell
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Cancelling 10/2 Meeting.
No updates, plan for next meeting on 10/16.
No updates, plan for next meeting on 10/16.
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By
Matt Cockrell
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Meeting 9/18
We will be meeting today. Tao will present his slides from the CHIPS Alliance WS on 9/17. See you in 5 mins!
We will be meeting today. Tao will present his slides from the CHIPS Alliance WS on 9/17. See you in 5 mins!
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By
Matt Cockrell
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Cancelling 9/4 meeting
Cancelling this meeting - not a working day for Google. For the next meeting we will have an update on the CI flow.
Cancelling this meeting - not a working day for Google. For the next meeting we will have an update on the CI flow.
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By
Matt Cockrell
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Cancelling 8/21
No significant updates. We will reconvene on 9/4. -- Matt
No significant updates. We will reconvene on 9/4. -- Matt
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By
Matt Cockrell
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Canceling 7/24 Meeting
We are canceling tomorrows meeting. Tao will send out newsletter with updates.
We are canceling tomorrows meeting. Tao will send out newsletter with updates.
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By
Matt Cockrell
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CHIPS Alliance riscv-dv Workgroup @ Fri, Jul 10, 2020 9:00am – 10:00am (GMT-07)
Hi All, Meeting is on this week. Here's the agenda I have right now: - General WG update: CA github, mail group etc. - Vector extension implementation update - Python based generator update Feel free
Hi All, Meeting is on this week. Here's the agenda I have right now: - General WG update: CA github, mail group etc. - Vector extension implementation update - Python based generator update Feel free
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By
Tao Liu
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next meetings
2 messages
I look at https://lists.chipsalliance.org/g/riscv-dv-wg but I cant see any form of calendar or notification as to when the next meetings are. can you let me know when the next ones are scheduled for,
I look at https://lists.chipsalliance.org/g/riscv-dv-wg but I cant see any form of calendar or notification as to when the next meetings are. can you let me know when the next ones are scheduled for,
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By
Simon Davidmann Imperas
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