Re: [interconnects-wg] Advanced Interface Bus repository is live


David Kehlet
 

Hi G S,

 

I intend to continue CHIPS Alliance and Intel in alignment in general.  Importantly, Intel is committed to compatibility with chiplets made to the current spec, much like PCIe Gen1/2/3/4/5 supports earlier versions.  This makes sense for all of us given the very substantial investment in the portfolio of chiplets from multiple companies.

 

Check out page 13 of this presentation:

https://github.com/chipsalliance/aib-phy-hardware/blob/master/docs/dkehlet_ocp_odsa_workshop_061019_v3.pdf

It describes the technology drivers for the future of AIB.  I plan to elaborate on these soon to gain feedback from the CHIPS Alliance members towards a 2.0 specification.  To your point about spending effort on AIB enhancements, yes for a 2.0 that is likely faster, lower voltage and more dense you will likely see benefits in using it.

 

I’m happy to have discussion about this with you, just let me know.

 

Dave

 

From: G S Madhusudan <mail@...>
Sent: Thursday, January 30, 2020 7:12 PM
To: Kehlet, David <david.kehlet@...>
Cc: technical-discuss@...; interconnects-wg@...
Subject: Re: [interconnects-wg] Advanced Interface Bus repository is live

 

David,

I had asked this question earlier when AIB was Intel internal . I know Intel has a roadmap for AIB variants internally. Will Chips Alliance have its own roadmap or will we be tracking Intel's roadmap. We plan to use AIB extensively for hpc designs , so would be useful to know if we need to spend efforts on AIB enhancements.

 

Regards

G S Madhusudan

 

On Fri, 31 Jan, 2020, 4:35 AM David Kehlet, <david.kehlet@...> wrote:

Hello, the Advanced Interface Bus (AIB) repo is migrated and live under CHIPS Alliance at

https://github.com/chipsalliance/aib-phy-hardware

 

The AIB spec in the docs directory now wears a CHIPS Alliance logo as well. The old github.com/intel site now has this readme:

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