Re: SweRV on Zedboard?

Zvonimir Bandic
 

Anupam,

 

My best guess is use the swerv_openocd.cfg to connect SweRV core using openOCD.

 

https://github.com/westerndigitalcorporation/swerv_eh1_fpga/blob/master/software/bsp/swerv_openocd.cfg     

 

(we will work on an update of FPGA ports, and put it on CHIPS Alliance). Also, check FuseSOC by Olof, as FuseSOC supports SweRV and Debug as well.

 

Thanks,

Z.

 

From: technical-discuss@... <technical-discuss@...> On Behalf Of ab0@...
Sent: Wednesday, October 9, 2019 10:17 PM
To: technical-discuss@...
Subject: [technical-discuss] SweRV on Zedboard?

 

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Has anyone tried to put SweRV on Zedboard? Any luck, making it work?
We have reviewed this link but it doesn't help : https://github.com/westerndigitalcorporation/swerv_eh1_fpga

 

Here is our status as per our engineers ...

"We are able to port the swerv core onto the Zedboard. After this we are making a simple "hello world" application to upload onto RISCV core.

To upload this application we are using openocd as debugging tool. So we are successfully able to communicate with jtag-smt2 module on zedboard using openocd i.e by giving jtag-smt2 configuration file as parameter in openocd. After that we need to upload a sample application on SweRV core in PL section, so we need core specific configuration file which we don't have. So what are the changes to be made in core configuration file which is compatible with RISCV core?

For Zed-board we are using "zynq-7000.cfg" as in file ARM CORTEX A9 configurations are specified. How do we remove those and add RISCV configuration for PL section?
"

Any pointer or help will be greatly appreciated.
Anupam

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