Date   
Re: [interconnects-wg] Advanced Interface Bus repository is live

David Kehlet
 

Hi G S,

 

I intend to continue CHIPS Alliance and Intel in alignment in general.  Importantly, Intel is committed to compatibility with chiplets made to the current spec, much like PCIe Gen1/2/3/4/5 supports earlier versions.  This makes sense for all of us given the very substantial investment in the portfolio of chiplets from multiple companies.

 

Check out page 13 of this presentation:

https://github.com/chipsalliance/aib-phy-hardware/blob/master/docs/dkehlet_ocp_odsa_workshop_061019_v3.pdf

It describes the technology drivers for the future of AIB.  I plan to elaborate on these soon to gain feedback from the CHIPS Alliance members towards a 2.0 specification.  To your point about spending effort on AIB enhancements, yes for a 2.0 that is likely faster, lower voltage and more dense you will likely see benefits in using it.

 

I’m happy to have discussion about this with you, just let me know.

 

Dave

 

From: G S Madhusudan <mail@...>
Sent: Thursday, January 30, 2020 7:12 PM
To: Kehlet, David <david.kehlet@...>
Cc: technical-discuss@...; interconnects-wg@...
Subject: Re: [interconnects-wg] Advanced Interface Bus repository is live

 

David,

I had asked this question earlier when AIB was Intel internal . I know Intel has a roadmap for AIB variants internally. Will Chips Alliance have its own roadmap or will we be tracking Intel's roadmap. We plan to use AIB extensively for hpc designs , so would be useful to know if we need to spend efforts on AIB enhancements.

 

Regards

G S Madhusudan

 

On Fri, 31 Jan, 2020, 4:35 AM David Kehlet, <david.kehlet@...> wrote:

Hello, the Advanced Interface Bus (AIB) repo is migrated and live under CHIPS Alliance at

https://github.com/chipsalliance/aib-phy-hardware

 

The AIB spec in the docs directory now wears a CHIPS Alliance logo as well. The old github.com/intel site now has this readme:

Re: [interconnects-wg] Advanced Interface Bus repository is live

Mr. G Madhusudan <mail@...>
 

David,
I had asked this question earlier when AIB was Intel internal . I know Intel has a roadmap for AIB variants internally. Will Chips Alliance have its own roadmap or will we be tracking Intel's roadmap. We plan to use AIB extensively for hpc designs , so would be useful to know if we need to spend efforts on AIB enhancements.

Regards
G S Madhusudan

On Fri, 31 Jan, 2020, 4:35 AM David Kehlet, <david.kehlet@...> wrote:

Hello, the Advanced Interface Bus (AIB) repo is migrated and live under CHIPS Alliance at

https://github.com/chipsalliance/aib-phy-hardware

 

The AIB spec in the docs directory now wears a CHIPS Alliance logo as well. The old github.com/intel site now has this readme:

Re: Advanced Interface Bus repository is live

Zvonimir Bandic
 

Awesome!

 

From: interconnects-wg@... <interconnects-wg@...> On Behalf Of David Kehlet
Sent: Thursday, January 30, 2020 3:05 PM
To: technical-discuss@...; interconnects-wg@...
Subject: [interconnects-wg] Advanced Interface Bus repository is live

 

CAUTION: This email originated from outside of Western Digital. Do not click on links or open attachments unless you recognize the sender and know that the content is safe.

 

Hello, the Advanced Interface Bus (AIB) repo is migrated and live under CHIPS Alliance at

https://github.com/chipsalliance/aib-phy-hardware

 

The AIB spec in the docs directory now wears a CHIPS Alliance logo as well. The old github.com/intel site now has this readme:

Advanced Interface Bus repository is live

David Kehlet
 

Hello, the Advanced Interface Bus (AIB) repo is migrated and live under CHIPS Alliance at

https://github.com/chipsalliance/aib-phy-hardware

 

The AIB spec in the docs directory now wears a CHIPS Alliance logo as well. The old github.com/intel site now has this readme:

Re: CHIPS Alliance ASCII logo

 

Reviving an old thread here, but on Friday I posted the CHIPS Alliance artwork, and included your ASCII art, Olof.  Thanks for doing this!


Brian

On Fri, Aug 16, 2019 at 2:50 AM Olof Kindgren <olof@...> wrote:
Ahhh! I didn't realize Courier new was fixed width. Yes, that's what I meant. This is what it looks like in a terminal

chips_ascii.png


Den tors 15 aug. 2019 kl 17:53 skrev Zvonimir Bandic <zvonimir.bandic@...>:

I think you think this -  I set the font to Courier New, that worked. I say it looks great!
    __
  []  []-o CHIPS
o-[]  []
  []  []-o ALLIANCE
o-[]__[]

 

From: technical-discuss@... <technical-discuss@...> On Behalf Of Olof Kindgren
Sent: Thursday, August 15, 2019 12:53 AM
To: technical-discuss@...
Subject: [technical-discuss] CHIPS Alliance ASCII logo

 

Hi,

With the lack of a general catch-all mailing list I'm taking the liberty to post here. As part of my work on SweRVolf I was thinking it would be nice to display an ASCII boot logo in the demo applications for branding purposes, so I put together this:

    __
  []  []-o CHIPS
o-[]  []
  []  []-o ALLIANCE
o-[]__[]

(haven't figured out how to set a monospaced font in this mailing list interface, so you will have to do that yourselves)

I think it's pretty niffty, but as I'm a terrible graphical designer it would be nice to get some input before setting it free.

//Olof



--

Brian Warner
The Linux Foundation
+1 724 301-6171

reply for membership

"李天瑞
 

Re: SweRV on Zedboard?

Zvonimir Bandic
 

Anupam,

 

My best guess is use the swerv_openocd.cfg to connect SweRV core using openOCD.

 

https://github.com/westerndigitalcorporation/swerv_eh1_fpga/blob/master/software/bsp/swerv_openocd.cfg     

 

(we will work on an update of FPGA ports, and put it on CHIPS Alliance). Also, check FuseSOC by Olof, as FuseSOC supports SweRV and Debug as well.

 

Thanks,

Z.

 

From: technical-discuss@... <technical-discuss@...> On Behalf Of ab0@...
Sent: Wednesday, October 9, 2019 10:17 PM
To: technical-discuss@...
Subject: [technical-discuss] SweRV on Zedboard?

 

CAUTION: This email originated from outside of Western Digital. Do not click on links or open attachments unless you recognize the sender and know that the content is safe.

 

Has anyone tried to put SweRV on Zedboard? Any luck, making it work?
We have reviewed this link but it doesn't help : https://github.com/westerndigitalcorporation/swerv_eh1_fpga

 

Here is our status as per our engineers ...

"We are able to port the swerv core onto the Zedboard. After this we are making a simple "hello world" application to upload onto RISCV core.

To upload this application we are using openocd as debugging tool. So we are successfully able to communicate with jtag-smt2 module on zedboard using openocd i.e by giving jtag-smt2 configuration file as parameter in openocd. After that we need to upload a sample application on SweRV core in PL section, so we need core specific configuration file which we don't have. So what are the changes to be made in core configuration file which is compatible with RISCV core?

For Zed-board we are using "zynq-7000.cfg" as in file ARM CORTEX A9 configurations are specified. How do we remove those and add RISCV configuration for PL section?
"

Any pointer or help will be greatly appreciated.
Anupam

SweRV on Zedboard?

ab0@...
 

Has anyone tried to put SweRV on Zedboard? Any luck, making it work?
We have reviewed this link but it doesn't help : https://github.com/westerndigitalcorporation/swerv_eh1_fpga

 

Here is our status as per our engineers ...

"We are able to port the swerv core onto the Zedboard. After this we are making a simple "hello world" application to upload onto RISCV core.

To upload this application we are using openocd as debugging tool. So we are successfully able to communicate with jtag-smt2 module on zedboard using openocd i.e by giving jtag-smt2 configuration file as parameter in openocd. After that we need to upload a sample application on SweRV core in PL section, so we need core specific configuration file which we don't have. So what are the changes to be made in core configuration file which is compatible with RISCV core?

For Zed-board we are using "zynq-7000.cfg" as in file ARM CORTEX A9 configurations are specified. How do we remove those and add RISCV configuration for PL section?
"

Any pointer or help will be greatly appreciated.
Anupam

SweRV micro architecture

rajoo gupta
 

Hi All,

Understanding the micro-architecture of SweRV has been a tough task for me. It would be really helpful if any more documents could be released or sent to me for further understanding

Request for sweRV micro architecture

rajoo gupta
 

Hi All,

I have been an active member following the SweRV development since the past 4 months.
I have a keen interest in the RISC-V architecture since its open source release.
understanding the micro-architecture of SweRV has been a tough task for me. IT would be really helpful if any more documents could be released or sent to me for further understanding.

 
Thanks & Regards
Rajoo Kumar Gupta

Re: CHIPS Alliance ASCII logo

Olof Kindgren
 

Ahhh! I didn't realize Courier new was fixed width. Yes, that's what I meant. This is what it looks like in a terminal

chips_ascii.png


Den tors 15 aug. 2019 kl 17:53 skrev Zvonimir Bandic <zvonimir.bandic@...>:

I think you think this -  I set the font to Courier New, that worked. I say it looks great!
    __
  []  []-o CHIPS
o-[]  []
  []  []-o ALLIANCE
o-[]__[]

 

From: technical-discuss@... <technical-discuss@...> On Behalf Of Olof Kindgren
Sent: Thursday, August 15, 2019 12:53 AM
To: technical-discuss@...
Subject: [technical-discuss] CHIPS Alliance ASCII logo

 

Hi,

With the lack of a general catch-all mailing list I'm taking the liberty to post here. As part of my work on SweRVolf I was thinking it would be nice to display an ASCII boot logo in the demo applications for branding purposes, so I put together this:

    __
  []  []-o CHIPS
o-[]  []
  []  []-o ALLIANCE
o-[]__[]

(haven't figured out how to set a monospaced font in this mailing list interface, so you will have to do that yourselves)

I think it's pretty niffty, but as I'm a terrible graphical designer it would be nice to get some input before setting it free.

//Olof

Re: CHIPS Alliance ASCII logo

Zvonimir Bandic
 

I think you think this -  I set the font to Courier New, that worked. I say it looks great!
    __
  []  []-o CHIPS
o-[]  []
  []  []-o ALLIANCE
o-[]__[]

 

From: technical-discuss@... <technical-discuss@...> On Behalf Of Olof Kindgren
Sent: Thursday, August 15, 2019 12:53 AM
To: technical-discuss@...
Subject: [technical-discuss] CHIPS Alliance ASCII logo

 

Hi,

With the lack of a general catch-all mailing list I'm taking the liberty to post here. As part of my work on SweRVolf I was thinking it would be nice to display an ASCII boot logo in the demo applications for branding purposes, so I put together this:

    __
  []  []-o CHIPS
o-[]  []
  []  []-o ALLIANCE
o-[]__[]

(haven't figured out how to set a monospaced font in this mailing list interface, so you will have to do that yourselves)

I think it's pretty niffty, but as I'm a terrible graphical designer it would be nice to get some input before setting it free.

//Olof

CHIPS Alliance ASCII logo

Olof Kindgren
 

Hi,

With the lack of a general catch-all mailing list I'm taking the liberty to post here. As part of my work on SweRVolf I was thinking it would be nice to display an ASCII boot logo in the demo applications for branding purposes, so I put together this:

    __
  []  []-o CHIPS
o-[]  []
  []  []-o ALLIANCE
o-[]__[]

(haven't figured out how to set a monospaced font in this mailing list interface, so you will have to do that yourselves)

I think it's pretty niffty, but as I'm a terrible graphical designer it would be nice to get some input before setting it free.

//Olof