David, I had asked this question earlier when AIB was Intel internal . I know Intel has a roadmap for AIB variants internally. Will Chips Alliance have its own roadmap or will we be tracking Intel's r

Hello, the Advanced Interface Bus (AIB) repo is migrated and live under CHIPS Alliance at https://github.com/chipsalliance/aib-phy-hardware The AIB spec in the docs directory now wears a CHIPS Allianc

Hi, With the lack of a general catch-all mailing list I'm taking the liberty to post here. As part of my work on SweRVolf I was thinking it would be nice to display an ASCII boot logo in the demo appl

Has anyone tried to put SweRV on Zedboard? Any luck, making it work? We have reviewed this link but it doesn't help : https://github.com/westerndigitalcorporation/swerv_eh1_fpga Here is our status as

Hi All, Understanding the micro-architecture of SweRV has been a tough task for me. It would be really helpful if any more documents could be released or sent to me for further understanding

Hi All, I have been an active member following the SweRV development since the past 4 months. I have a keen interest in the RISC-V architecture since its open source release. understanding the micro-a